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D a t a S h e e t , Rev. 0.87, J u n e 2 0 0 4
HYS64T32000[G/H]U-[3.7/5]-A HYS[64/72]T64000[G/H]U-[3.7/5]-A HYS[64/72]T128020[G/H]U-[3.7/5]-A
240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM
Memory Products
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stop
thinking.
The information in this document is subject to change without notice. Edition 2004-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 0.87, J u n e 2 0 0 4
HYS64T32000[G/H]U-[3.7/5]-A HYS[64/72]T64000[G/H]U-[3.7/5]-A HYS[64/72]T128020[G/H]U-[3.7/5]-A
240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM
Memory Products
Never
stop
thinking.
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A Revision History: Previous Revision: Page all chapter 5 all Rev. 0.87 Rev. 0.84 2004-06 2003-09
Subjects (major changes since last revision) New template add currents updated timings
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Table of Contents 1 1.1 1.2 1.3 2 3 3.1 4 4.1 4.2 5 5.1 6 7 7.1 7.2 7.3 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 9
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 27 ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
IDD Specifications and Conditions
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC Timing Parameter by Speed Grade (Component level data, for reference only) . . . . . . . . . . . . . 28 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 63 64
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data Sheet
5
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
1
Overview
This chapter gives an overview of the 1.8 V 240-pin Unbuffered DDR2 SDRAM Modules, 256 MByte, 512 MByte & 1 GByte ECC and non-ECC Modules and describes its main characteristics.
1.1
*
Features
* * * * * * * Programmable CAS Latencies (3, 4 & 5), Burst Length (8 & 4) and Burst Type Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_1.8 compatible OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237) Based on JEDEC standard reference card layouts Raw Card "A", "B" & "C"
* *
*
240-pin ECC and Non-ECC Unbuffered 8-Byte Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications One rank 32M x 64, 64M x 64, 64M x 72 and two ranks 128M x 64 and 128M x 72 organization JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply 256 ,512 MByte and 1GByte modules built with 512Mb DDR2 SDRAMs in 60-ball (P-TFBGA-60) and 84-ball FBGA (P-TFBGA-84) chipsize packages Performance
Table 1
Speed Grade Indicator Component Speed Grade Module Speed Grade Max. Clock Frequency @ CL = 3 Max. Clock Frequency @ CL = 4 & 5
-5 DDR2-400 PC2-3200 200 200
--3.7 DDR2-533 PC2-4200 200 266
Unit -- -- MHz MHz
1.2
Description
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for ECC and Non-ECC applications. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The INFINEON HYS[64/72]Txxxx0[G/H]U module family are low profile Unbuffered DIMM modules with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 32M x 64 (256MB), 64M x 64 (512MB) and 128M x 64 (1024MB) and as ECC-modules in 64M x 72 (512MB) and 128M x 72 (1024MB) organisation and density, intended for mounting into 240 pin connector sockets.
Data Sheet
6
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information Compliance Code Description SDRAM Technology 512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8 512 Mbit (x8)
Product Type PC2-3200 HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A HYS64T128020GU-5-A HYS72T128020GU-5-A
256MB 1Rx16 PC2-3200U-333-11-C0 512MB 1Rx8 PC2-3200U-333-11-A0 512MB 1Rx8 PC2-3200E-333-11-A0 1GB 2Rx8 PC2-3200U-333-11-B0 1GB 2Rx8 PC2-3200E-333-11-B0
1 Rank, Non-ECC 1 Rank, Non-ECC 1 Rank, ECC 2 Ranks, Non-ECC 2 Ranks, ECC
HYS64T32000HU-5-A HYS64T64000HU-5-A HYS72T64000HU-5-A HYS64T128020HU-5-A HYS72T128020HU-5-A PC2-4200 HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A HYS64T128020GU-3.7-A HYS72T128020GU-3.7-A
256MB 1Rx16 PC2-3200U-333-11-C0 512MB 1Rx8 PC2-3200U-333-11-A0 512MB 1Rx8 PC2-3200E-333-11-A0 1GB 2Rx8 PC2-3200U-333-11-B0 1GB 2Rx8 PC2-3200E-333-11-B0 256MB 1Rx16 PC2-4200U-444-11-C0 512MB 1Rx8 PC2-4200U-444-11-A0 512MB 1Rx8 PC2-4200E-444-11-A0 1GB 2Rx8 PC2-4200U-444-11-B0 1GB 2Rx8 PC2-4200E-444-11-B0
1 rank, Non-ECC 1 rank, Non-ECC 1 rank, ECC 2 ranks, Non-ECC 2 ranks, ECC 1 rank, Non-ECC 1 rank, Non-ECC 1 rank, ECC 2 ranks, Non-ECC 2 ranks, ECC
512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8 512 Mbit (x8)
HYS64T32000HU-3.7-A HYS72T64000HU-3.7-A HYS64T64000HU-3.7-A HYS64T128020HU-3.7-A HYS72T128020HU-3.7-A Note:
256MB 1Rx16 PC2-4200U-444-11-C0 512MB 1Rx8 PC2-4200E-444-11-A0 512MB 1Rx8 PC2-4200U-444-11-A0 1GB 2Rx8 PC2-4200U-444-11-B0 1GB 2Rx8 PC2-4200E-444-11-B0
1 rank, Non-ECC 1 rank, ECC 1 rank, Non-ECC 2 ranks, Non-ECC 2 ranks, ECC
512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8)
1. All part numbers end with a place code, designating the silicon die revision. Example: HYS72T64000GU-5-A, indicating Rev. A dice are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see section 8 of this datasheet. 2. The Compliance Code is printed on the module label and describes the speed grade, f.e. "PC2-
4200U-44410-C", where 4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and "44410" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "C".
Data Sheet
7
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 3 DIMM Density 256 MB 512 MB 512 MB 1 GB 1 GB Table 4
Address Format Module Organization 32M x64 64M x64 64M x72 2 x 64M x72 2 x 64M x72 Memory Ranks 1 1 1 2 2 ECC/ Non-ECC Non-ECC Non-ECC ECC Non-ECC ECC # of SDRAMs 4 8 9 16 18 # of row/bank/columns bits 13/2/10 14/2/10 14/2/10 14/2/10 14/2/10 Raw Card C A A B B
Components on Modules1) DIMM Density 256 MB 256 MB 512 MB 512 MB 512 MB 512 MB 1 GB 1 GB 1 GB 1 GB
2)
Part Number HYS64T32000GU HYS64T32000HU HYS64T64000HU HYS64T64000GU
2)
DRAM components reference datasheet HYB18T512160AC HYB18T512160AF HYB18T512800AF
2)
DRAM Density 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit
DRAM Organisation 32M x16 32M x16 64Mb x8 64Mb x8 64Mb x8 64Mb x8 64Mb x8 64Mb x8 64Mb x8 64Mb x8
HYB18T512800AC
2)
HYS72T64000GU HYS72T64000HU2) HYS64T128020GU HYS64T128020HU HYS72T128020HU
2)
HYB18T512800AC HYB18T512800AF2) HYB18T1G800AC HYB18T1G800AF HYB18T1G800AF
2)
HYS72T128020GU
2)
HYB18T1G800AC
2)
1) For a detailed description of all functionalities of the DRAM components on these modules see the referenced component datasheet. 2) Green Product
Data Sheet
8
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
1.3
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules (x64) and Figure 2 for ECC modules (x72). Table 5 Pin# Clock Signals 185 137 220 186 138 221 52 171 CK0 CK1 CK2 CK0 CK1 CK2 CKE0 CKE1 NC Control Signals 193 76 S0 S1 NC 192 74 73 Address Signals 71 190 54 BA0 BA1 BA2 NC 188 183 63 182 61 60 180 58 179 177 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I I I NC I I I I I I I I I I SSTL SSTL SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Bank Address Bus 2 Note: greater than 512Mb DDR2 SDRAMS Note: less than 1Gb DDR2 SDRAMS Address Bus 12:0 Bank Address Bus 1:0 RAS CAS WE I I NC I I I SSTL SSTL -- SSTL SSTL SSTL Chip Select Rank 0 Chip Select Rank 1 Note: 2 Ranks module Note: 1 Rank module Row Address Strobe Column Address Strobe Write Enable I I I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- Clock Enable Rank 0 Clock Enable Rank 1 Note: 2 Ranks module Note: 1 Rank module Complement Clock Signals 2:0 Clock Signals 2:0 Pin Configuration of UDIMM Name Pin Buffer Function Type Type
Data Sheet
9
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 70 57 176 196 Pin Configuration of UDIMM (cont'd) Name A10 AP A11 A12 A13 NC Pin Buffer Function Type Type I I I I I NC SSTL SSTL SSTL SSTL SSTL -- Address Signal 13 Note: 1 Gbit based module and 512M x4/x8 Note: 1. Module based on 1 Gbit x16 2. Module based on 512 Mbit x16 or smaller 174 A14 NC Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 I NC SSTL -- Address Signal 14 Note: Modules based on 2 Gbit Note: Modules based on 1 Gbit or smaller Address Bus 12:0
Data Sheet
10
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Pin Configuration of UDIMM (cont'd) Name DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0
Data Sheet
11
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# Check Bit Signal 42 CB0 NC 43 CB1 NC 48 CB2 NC 49 CB3 NC 161 CB4 NC 162 CB5 NC 167 CB6 NC 168 CB7 NC Data Strobe Bus 7 16 28 37 84 93 105 114 45 6 15 27 36 83 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS0 DQS1 DQS2 DQS3 DQS4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Complement Data Strobe Bus 8:0 Note: See block diagram for corresponding DQ signals Data Strobe Bus 8:0 Note: See block diagram for corresponding DQ signals I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- Check Bit 0 Note: ECC type module only Note: Non-ECC module Check Bit 1 Note: ECC type module only Note: Non-ECC module Check Bit 2 Note: ECC type module only Note: Non-ECC module Check Bit 3 Note: ECC type module only Note: Non-ECC module Check Bit 4 Note: ECC type module only Note: Non-ECC module Check Bit 5 Note: ECC type module only Note: Non-ECC module Check Bit 6 Note: ECC type module only Note: Non-ECC module Check Bit 7 Note: ECC type module only Note: Non-ECC module Pin Configuration of UDIMM (cont'd) Name Pin Buffer Function Type Type
Data Sheet
12
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 92 104 113 46 Data Mask Signals 125 134 146 155 202 211 223 232 164 EEPROM 120 119 239 240 101 Power Supplies 1 SCL SDA SA0 SA1 SA2 I I/O I I I CMOS Serial Bus Clock OD CMOS CMOS I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Power Supply Ground Plane Serial Bus Data CMOS Slave Address Select Bus 2:0 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Bus 8:0 Pin Configuration of UDIMM (cont'd) Name DQS5 DQS6 DQS7 DQS8 Pin Buffer Function Type Type I/O I/O I/O I/O SSTL SSTL SSTL SSTL Complement Data Strobe Bus 8:0
VREF AI -- 238 VDDSPD PWR -- 51,56,62,72,75,78,170,175,181, VDDQ PWR --
191,194 53,59,64,67,69,172,178,184,187 VDD 189,197 2,5,8,11,14,17,20,23,26,29,32, 35,38,41,44,47,50,65,66,79,82, 85,88,91,94,97,100,103,106, 109,112,115,118,121,124,127, 130,133,136,139,142,145,148, 151,154,157,160,163,166,169, 198,201,204,207,210,213,216, 219,222,225,228,231,234,237 Other Pins 195 77 18,19,55,68,102,126,135,147, 156,165,173,203,212, 224,233 ODT0 ODT1 NC NC NC NC -- -- PWR -- GND --
VSS
On-Die Termination Control 0 On-Die Termination Control 1 Note: 1 Rank modules Not connected Note: Pins not connected on Infineon UDIMMs
Data Sheet
13
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 6 I O I/O AI PWR GND NC
Abbreviations for Buffer Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Abbreviation
Table 7 SSTL LV-CMOS CMOS OD
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation
Data Sheet
14
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
VREF - Pin 001 DQ0 V SS DQ2 V SS DQ9 - Pin 003 - Pin 005 - Pin 009 - Pin 011 - Pin 013
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 NC V SS DQ11 DQ16 V SS DQS2 DQ18 V SS DQ25 DQS3 V SS DQ27 NC V SS NC NC V SS
- Pin 002 - Pin 004 - Pin 006 - Pin 008 - Pin 010 - Pin 012 - Pin 014 - Pin 016 - Pin 018 - Pin 020 - Pin 022 - Pin 024
Pin 122 - DQ4 Pin 124 - V SS Pin 126 - NC Pin 128 - DQ6 Pin 130 - V SS Pin 132 - DQ13 Pin 134 - DM1 Pin 136 - V SS Pin 138 - CK1 Pin 140 - DQ14 Pin 142 - V SS Pin 144 - DQ21
Pin 121 - V SS Pin 123 - DQ5 Pin 125 - DM0 Pin 127 - V SS Pin 129 - DQ7 Pin 131 - DQ12 Pin 133 - V SS Pin 135 - NC Pin 137 - CK1 Pin 139 - V SS Pin 141 - DQ15 Pin 143 - DQ20 Pin 145 - V SS Pin 147 - NC Pin 149 - DQ22 Pin 151 - V SS Pin 153 - DQ29 Pin 155 - DM3 Pin 157 - V SS Pin 159 - DQ31 Pin 161 - NC Pin 163 - V SS Pin 165 - NC Pin 167 - NC Pin 169 - V SS Pin 171 - CKE1 Pin 173 - NC Pin 175 - V DDQ Pin 177 - A9 Pin 179 - A8 Pin 181 - V DDQ Pin 183 - A1
DQS0 - Pin 007
DQS1 - Pin 015 V SS - Pin 017 NC - Pin 019 DQ10 - Pin 021 - Pin 023 V
SS
DQ17 - Pin 025 DQS2 - Pin 027 V SS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 V SS - Pin 035 DQS3 - Pin 037 DQ26 - Pin 039 V SS NC NC V SS NC V DD NC A11 V DD A4 A2 - Pin 041 - Pin 043 - Pin 045 - Pin 047 - Pin 049 - Pin 053 - Pin 055 - Pin 057 - Pin 059 - Pin 061 - Pin 063
FRONTSIDE
- Pin 030 - Pin 032 - Pin 034 - Pin 036 - Pin 038 - Pin 040 - Pin 042 - Pin 044 - Pin 046 - Pin 048 - Pin 050
BACKSIDE
- Pin 026 - Pin 028
Pin 146 - DM2 Pin 148 - V SS Pin 150 - DQ23 Pin 152 - DQ28 Pin 154 - V SS Pin 156 - NC Pin 158 - DQ30 Pin 160 - V SS Pin 162 - NC Pin 164 - NC Pin 166 - V SS Pin 168 - NC Pin 170 - V DDQ Pin 172 - V DD Pin 174 - A14 Pin 176 - A12 Pin 178 - V DD Pin 180 - A6 Pin 182 - A3 Pin 184 - V DD
V DDQ - Pin 051
CKE0 - Pin 052 NC/BA2 - Pin 054 - Pin 056 V DDQ A7 A5 V DDQ V DD - Pin 058 - Pin 060 - Pin 062 - Pin 064
V SS V DD V DD BA0 WE
- Pin 065 - Pin 067 - Pin 069 - Pin 071 - Pin 073
V SS
- Pin 066
NC - Pin 068 A10/AP - Pin 070 - Pin 072 V
DDQ
Pin 186 - CK0 Pin 188 - A0 Pin 190 - BA1 Pin 192 - RAS Pin 194 - V DDQ Pin 196 - NC/A13 Pin 198 - V SS Pin 200 - DQ37 Pin 202 - DM4 Pin 204 - V SS Pin 206 - DQ39 Pin 208 - DQ44 Pin 210 - V SS Pin 212 - NC Pin 214 - DQ46 Pin 216 - V SS Pin 218 - DQ53 Pin 220 - CK2 Pin 222 - V SS Pin 224 - NC Pin 226 - DQ54 Pin 228 - V SS Pin 230 - DQ61 Pin 232 - DM7 Pin 234 - V SS Pin 236 - DQ63 Pin 238 Pin 240 V DDSPD SA1
Pin 185 - CK0 Pin 187 - V DD Pin 189 - V DD Pin 191 - V DDQ Pin 193 - S0 Pin 195 - ODT0 Pin 197 - V DD Pin 199 - DQ36 Pin 201 - V SS Pin 203 - NC Pin 205 - DQ38 Pin 207 - V SS Pin 209 - DQ45 Pin 211 - DM5 Pin 213 - V SS Pin 215 - DQ47 Pin 217 - DQ52 Pin 219 - V SS Pin 221 - CK2 Pin 223 - DM6 Pin 225 - V SS Pin 227 - DQ55 Pin 229 - DQ60 Pin 231 - V SS Pin 233 - NC Pin 235 - DQ62 Pin 237 Pin 239 V SS SA0 MPPT0150
V DDQ - Pin 075 ODT1 - Pin 077 V SS - Pin 079 DQ33 - Pin 081 DQS4 - Pin 083 V SS - Pin 085 DQ35 - Pin 087 DQ40 - Pin 089 V SS - Pin 091 DQS5 - Pin 093 DQ42 - Pin 095 V SS - Pin 097 DQ49 - Pin 099 SA2 - Pin 101 V SS - Pin 103 DQS6 - Pin 105 DQ50 - Pin 107 V SS - Pin 109 DQ57 - Pin 111 DQS7 - Pin 113 V SS SDA - Pin 115 - Pin 119 DQ59 - Pin 117
CAS NC/S1 V DDQ DQ32 V SS DQS4 DQ34 V SS DQ41 DQS5 V SS DQ43 DQ48 V SS NC DQS6 V SS DQ51 DQ56 V SS DQS7 DQ58 V SS SCL
- Pin 074 - Pin 076 - Pin 078 - Pin 080 - Pin 082 - Pin 084 - Pin 086 - Pin 088 - Pin 090 - Pin 092 - Pin 094 - Pin 096 - Pin 098 - Pin 100 - Pin 102 - Pin 104 - Pin 106 - Pin 108 - Pin 110 - Pin 112 - Pin 114 - Pin 116 - Pin 118 - Pin 120
Figure 1
Pin Configuration UDIMM x64 (240 Pin)
Data Sheet
15
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
VREF - Pin 001 DQ0 V SS DQ2 V SS DQ9 - Pin 003 - Pin 005 - Pin 009 - Pin 011 - Pin 013
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 NC V SS DQ11 DQ16 V SS DQS2 V SS V SS DQ25 DQS3 V SS DQ27 CB0 V SS DQS8 CB2 V SS CKE0
- Pin 002 - Pin 004 - Pin 006 - Pin 008 - Pin 010 - Pin 012 - Pin 014 - Pin 016 - Pin 018 - Pin 020 - Pin 022 - Pin 024
Pin 122 - DQ4 Pin 124 - V SS Pin 126 - NC Pin 128 - DQ6 Pin 130 - V SS Pin 132 - DQ13 Pin 134 - DM1 Pin 136 - NC Pin 138 - CK1 Pin 140 - DQ14 Pin 142 - V SS Pin 144 - DQ21 Pin 146 - DM2
Pin 121 - V SS Pin 123 - DQ5 Pin 125 - DM0 Pin 127 - V SS Pin 129 - DQ7 Pin 131 - DQ12 Pin 133 - V SS Pin 135 - NC Pin 137 - CK1 Pin 139 - V SS Pin 141 - DQ15 Pin 143 - DQ20 Pin 145 - V SS Pin 147 - NC Pin 149 - DQ22 Pin 151 - V SS Pin 153 - DQ29 Pin 155 - DM3 Pin 157 - V SS Pin 159 - DQ31 Pin 161 - CB4 Pin 163 - V SS Pin 165 - NC Pin 167 - CB6 Pin 169 - V SS Pin 171 - CKE1 Pin 173 - NC Pin 175 - V DDQ Pin 177 - A9 Pin 179 - A8 Pin 181 - V DDQ Pin 183 - A1
DQS0 - Pin 007
DQS1 - Pin 015 V SS - Pin 017 NC - Pin 019 DQ10 - Pin 021 - Pin 023 V SS DQ17 - Pin 025 DQS2 - Pin 027 V SS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 V SS - Pin 035 DQS3 - Pin 037 DQ26 - Pin 039 V SS CB1 - Pin 041 - Pin 043
FRONTSIDE
- Pin 030 - Pin 032 - Pin 034 - Pin 036 - Pin 038 - Pin 040 - Pin 042 - Pin 044 - Pin 046 - Pin 048 - Pin 050
BACKSIDE
- Pin 026 - Pin 028
Pin 148 - V SS Pin 150 - DQ23 Pin 152 - DQ28 Pin 154 - V SS Pin 156 - NC Pin 158 - DQ30 Pin 160 - V SS Pin 162 - CB5 Pin 164 - DM8 Pin 166 - V SS Pin 168 - CB7 Pin 170 - V DDQ Pin 172 - V DD Pin 174 - A14 Pin 176 - A12 Pin 178 - V DD Pin 180 - A6 Pin 182 - A3 Pin 184 - V DD
DQS8 - Pin 045 V SS - Pin 047 CB3 V DD NC A11 V DD A4 A2 - Pin 049 - Pin 053 - Pin 055 - Pin 057 - Pin 059 - Pin 061 - Pin 063 V DDQ - Pin 051
- Pin 052 NC/BA2 - Pin 054 - Pin 056 V DDQ A7 A5 V DDQ V DD - Pin 058 - Pin 060 - Pin 062 - Pin 064
V SS V DD V DD BA0 WE
- Pin 065 - Pin 067 - Pin 069 - Pin 071 - Pin 073
V SS
- Pin 066
NC - Pin 068 A10/AP - Pin 070 - Pin 072 V
DDQ
Pin 186 - CK0 Pin 188 - A0 Pin 190 - BA1 Pin 192 - RAS Pin 194 - V DDQ Pin 196 - NC/A13 Pin 198 - V SS Pin 200 - DQ37 Pin 202 - DM4 Pin 204 - V SS Pin 206 - DQ39 Pin 208 - DQ44 Pin 210 - V SS Pin 212 - NC Pin 214 - DQ46 Pin 216 - V SS Pin 218 - DQ53 Pin 220 - CK2 Pin 222 - V SS Pin 224 - NC Pin 226 - DQ54 Pin 228 - V SS Pin 230 - DQ61 Pin 232 - DM7 Pin 234 - V SS Pin 236 - DQ63 Pin 238 Pin 240 V DDSPD SA1
Pin 185 - CK0 Pin 187 - V DD Pin 189 - V DD Pin 191 - V DDQ Pin 193 - S0 Pin 195 - ODT0 Pin 197 - V DD Pin 199 - DQ36 Pin 201 - V SS Pin 203 - NC Pin 205 - DQ38 Pin 207 - V SS Pin 209 - DQ45 Pin 211 - DM5 Pin 213 - V SS Pin 215 - DQ47 Pin 217 - DQ52 Pin 219 - V SS Pin 221 - CK2 Pin 223 - DM6 Pin 225 - V SS Pin 227 - DQ55 Pin 229 - DQ60 Pin 231 - V SS Pin 233 - NC Pin 235 - DQ62 Pin 237 Pin 239 V SS SA0 MPPT0160
V DDQ - Pin 075 ODT1 - Pin 077 V SS - Pin 079 DQ33 - Pin 081 DQS4 - Pin 083 V SS - Pin 085 DQ35 - Pin 087 DQ40 - Pin 089 V SS V SS V SS - Pin 091 - Pin 095 - Pin 097 DQS5 - Pin 093
CAS NC/S1 V DDQ DQ32 V SS DQS4 DQ34 V SS DQ41 DQS5 V SS DQ43 DQ48 V SS NC DQS6 V SS DQ51 DQ56 V SS DQS7 DQ58 V SS SCL
- Pin 074 - Pin 076 - Pin 078 - Pin 080 - Pin 082 - Pin 084 - Pin 086 - Pin 088 - Pin 090 - Pin 092 - Pin 094 - Pin 096 - Pin 098 - Pin 100 - Pin 102 - Pin 104 - Pin 106 - Pin 108 - Pin 110 - Pin 112 - Pin 114 - Pin 116 - Pin 118 - Pin 120
DQ49 - Pin 099 SA2 - Pin 101 V SS - Pin 103 DQS6 - Pin 105 DQ50 - Pin 107 V SS - Pin 109 DQ57 - Pin 111 DQS7 - Pin 113 V SS SDA - Pin 115 - Pin 119 DQ59 - Pin 117
Figure 2
Pin Configuration UDIMM x72 (240 Pin)
Data Sheet
16
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 8 Symbol CK0-CKn, CK0-CKn
Input/Output Functional Description Type I Polarity Function Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Selects internal SDRAM memory bank Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data Input/Output pins The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers programmed appropriately. Power supplies for core, I/O, Serial Presence Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to to VDDSPD on the motherboard to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. Address pins used to select the Serial Presence Detect base address.
CKE0CKEn S0-Sn
I
Active High Active Low
I
RAS, CAS, I WE BA0-BAn ODT0ODTn A[9:0], A10/AP, A[12:11] I I I
Active Low -- Active High --
DQ[63:0] DM[8:0]
I/O I
-- Active High Cross point
DQS[8:0], DQS[8:0]
I/O
VDD, Supply -- VDDSPD, VSS
SDA I/O --
SCL SA0-SAn
I I
-- --
Data Sheet
17
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
2
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
Block Diagrams
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' 966 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 9''63' 9''9''4 95() 966 9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
'
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
'
'0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 6&/ 6'$ 6$ 6$
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 6&/ 6'$ $ $ $ :3
'
'
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03%7
Figure 3 Note 1. 2. 3. 4.
Block Diagram Raw Card A UDIMM (x64, 1 Rank, x8)
DQ,DQS,DQS,DM resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 5.1 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 9 Clock Input CK0,CKO CK1,CK1 CK2,CK3
Clock Signal Loads SDRAMs 2 3 3 Note
Data Sheet
18
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' 9''63' &$6 6'5$0V ' ' :( 6'5$0V ' ' 9''9''4 &.( 6'5$0V ' ' 95() 2'7 6'5$0V ' ' 966 966 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
6&/ 6'$ 6$ 9'' 63' ((3520 ( 6$ 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' ' '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 &% &% &% &% &% &% &% &%
6&/ 6'$ $ $ $ :3 9VV '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
(
'
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03%7
Figure 4 Note 1. 2. 3. 4.
Block Diagram Raw Card A UDIMM (x72, 1 Rank, x8)
DQ,DQS,DQS,DM,CB resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 5.1 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 10 Clock Input CK0,CK0 CK1,CK1 CK2,CK3
1)
Clock Signal Loads SDRAMs 3 3 3 Note
1)
2 SDRAMS for CK0 in case of non-ECC
Data Sheet
19
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
)
BA0 - BA2 A0 - An RAS CAS WE CKE 0 CKE 1 ODT 0 ODT 1
BA0 - BA2: SDRAMs D0 - D15 A0 - An: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 CKE 0: SDRAMs D0 - D7 CKE 1: SDRAMs D8 - D15 ODT 0: SDRAMs D0 - D7 ODT 0: SDRAMs D8 - D15 VSS
VDD,SPD VDD/VDDQ VREF VSS
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D15 VREF: SDRAMs D0 - D15 VSS: SDRAMs D0 - D15
SCL SDA SA0 SA1 VSS
SCL SDA A0 A1 A2 WP
E0
S0 S1 DM0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D8 DM4 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM6 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D4 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D12
CS
D1
CS
D9
CS
D5
CS
D13
CS
D2
CS
D10
CS
D6
CS
D14
CS
D3
CS
D11
CS
D7
CS
D15
Figure 5 Note 1. 2. 3. 4.
Block Diagram Raw Card B UDIMM (x64, 1 Rank, x8)
MPBT0130
DQ,DQS,DQS,DM,CB resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 7.5 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 11 Clock Input CK0,CK0 CK1,CK1 CK2,CK3
Clock Signal Loads SDRAMs 4 6 6 Note
Data Sheet
20
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
&.( &.( 2'7 2'7

6 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 &% &% &% &% &% &% &% &%
&.( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' 2'7 6'5$0V ' ' 966 ' '
%$ %$ $ $Q 5$6 &$6 :(
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' '
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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'0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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'
'0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 6&/ 6'$ $ $ $ :3 9VV
'
'
'
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9''63' 9''9''4 95() 966
03%7
Figure 6 Note: 1. 2. 3. 4.
Block Diagram Raw Card B UDIMM (x72, 1 Rank, x8)
DQ,DQS,DQS,DM,CB resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 7.5 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 12 Clock Input CK0,CK0 CK1,CK1 CK2,CK3
Clock Signal Loads SDRAMs 6 6 6 Note
Data Sheet
21
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 6&/ 6'$ 6$ 6$
966 6&/ 6'$ $ $ $ :3
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' (
9''63' 9''9''4 95() 966
9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
9VV
'0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
'
'0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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03%7
Figure 7 Note
Block Diagram Raw Card C UDIMM (x64, 1Rank, x16)
1. DQ, DQS, DM resistors are 22 5 % 2. BAn, An, RAS, CAS, WE resistors are 10 5 %
Data Sheet
22
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics
3
3.1
Table 13 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Limit Values min. max. 2.3 2.3 2.3 +100 95 C % V V - 0.5 - 1.0 - 0.5 -55 5 Unit
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage temperature range Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ THSTG HSTG
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 14 Parameter DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Barometric Pressure (operating & storage) Operating Conditions Symbol Limit Values min. max. +55 +95 +105 C C kPa
1)2)3)4)
Unit
Notes
TOPR TCASE
PBar
0 0 +69
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2) Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85C case temperature before initiating self-refresh operation. Table 15 Parameter Device Supply Voltage Output Supply Voltage Input Reference Voltage EEPROM Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1) Under all conditions,
Supply Voltage Levels and DC Operating Conditions Symbol Limit Values min. nom. 1.8 1.8 0.5 x VDDQ - - - max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V A
3)
Unit
Notes 1) 2)
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30 -5
VDDQ + 0.3 VREF - 0.125
5
VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations
in VDDQ. 3) Voltage for pin connector under test input of 0 V VIN VDDQ + 0.3 V; all othe pins at 0 V. Current is per pin Data Sheet 23
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
Table 16 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions1)2)
Symbol
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD1
IDD2P IDD2N
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
Distributed Refresh Current IDD5D tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
24
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions Table 16 Parameter
IDD Measurement Conditions1)2) (cont'd)
Symbol
IDD6 Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 C max.
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 17
IDD Specification
HYS64T128020GU-3.7-A HYS64T128020HU-3.7-A HYS72T128020GU-3.7-A HYS72T128020HU-3.7-A HYS64T32000GU-3.7-A HYS64T32000HU-3.7-A HYS64T64000GU-3.7-A HYS64T64000HU-3.7-A HYS72T64000GU-3.7-A HYS72T64000HU-3.7-A Unit Notes
Product Type
Organization
256MB x64 1 Rank -3.7
512MB x64 1 Rank -3.7 Max. 520 600 32 320 240 128 40 320 720 760 1040 48 32 1120
512MB x72 1 Rank -3.7 Max. 585 675 36 360 270 144 45 360 810 855 1170 54 36 1260
1GB x64 2 Ranks -3.7 Max. 552 632 64 640 480 256 80 640 752 792 1072 96 64 1152
1GB x72 2 Ranks -3.7 Max. 621 711 72 720 540 288 90 720 846 891 1206 108 72 1296 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)
Symbol
Max. 320 360 16 160 120 64 20 160 400 440 520 24 16 880
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
25
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 18
IDD Specification
HYS72T128020GU-5-A HYS72T128020HU-5-A HYS64T128020GU-5-A HYS64T128020HU-5-A HYS64T64000GU-5-A HYS64T64000HU-5-A HYS64T32000GU-5-A HYS64T32000HU-5-A HYS72T64000GU-5-A HYS72T64000HU-5-A Unit Notes
Product Type
Organization
256MB x64 1 Rank -5
512MB x64 1 Rank -5 Max. 440 480 32 256 200 104 40 280 560 600 960 48 32 1040
512MB x72 1 Rank -5 Max. 495 540 36 288 225 117 45 315 630 675 1080 54 36 1170
1GB x64 2 Ranks -5 Max. 472 512 64 512 400 208 80 560 592 632 992 96 64 1072
1GB x72 2 Ranks -5 Max. 531 576 72 576 450 234 90 630 666 711 1116 108 72 1206 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)
Symbol
Max. 280 300 16 128 100 52 20 140 340 360 480 24 16 840
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
26
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used: Table 19 Parameter
IDD Measurement Test Conditions
Symbol -5 PC2-3200 3-3-3 -3.7 PC2-4200 4-4-4 4 3.75 15 60 7.5 10 45 15 105 7.8 Unit
CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B x8 command delay x16 2) Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval 1) For modules based on x8 components 2) For modules based on x16 components
1)
CLmin tCKmin tRCDmin tRCmin tRRDmin tRRDmin tRASmin tRPmin tRFCmin tREFI
3 5 15 55 7.5 10 40 15 105 7.8
tCK
ns ns ns ns ns ns ns ns s
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tristate or driving 0 or 1, as long a ODT is enabled during a given period of time. Table 20 ODT current per terminated pin: EMRS(1) State Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING min. typ. 6 3 max. 7.5 3.75 Unit mA/DQ mA/DQ
IODTO
A6 = 0, A2 = 1 5 A6 = 1, A2 = 0 2.5
IODTT Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
A6 = 0, A2 = 1 10 A6 = 1, A2 = 0 5
12 6
15 7.5
mA/DQ mA/DQ
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
27
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
5.1
Table 21
Electrical Characteristics & AC Timings
AC Timing Parameter by Speed Grade (Component level data, for reference only)
AC Timing - Absolute Specifications -5 / -3.7 -5 DDR2-400 min. max. + 600 0.55 8000 8000 0.55 -3.7 DDR2-533 min. -500 2 0.45 5000 3750 3 0.45 max. +500 0.55 8000 8000 0.55 +450 WL +0.25 300 ps
1) 1) 1) 1)2) 1)3) 1) 1) 1) 1)
Symbol Parameter
Unit Notes
tAC tCCD tCH tCK tCKE tCL tDAL tDELAY tDH tDIPW tDQSCK tDQSL,H tDQSS tDQSQ tDS tDSH tDSS tHP tHZ tIH tIPW tIS tLZ(DQ) tLZ(DQS) tMRD tOIT tRAS tRC tRCD
DQ output access time from CK/CK CAS A to CAS B Command Period CK, CK high-level width Clock cycle time CKE minimum high and low pulse width CK, CK low-level width Minimum time clocks remain ON after CKE asynchronously drops low DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle) Write command to 1st DQS latching transition DQS-DQ skew (for DQS & associated DQ signals) DQ and DM input setup time DQS falling edge hold time from CLK (write cycle) DQS falling edge to CLK setup time (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time Address and control input setup time DQ low-impedance from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay (with and without Auto-Precharge) delay
- 600 2 0.45 5000 5000 3 0.45
tCK
tCK ps ps
tCK
tCK
Auto precharge write recovery + precharge time WR+tRP
H
WR+tRP -
tCK
ns ps
tIS+tCK+tI 400 0.35 - 500 0.35 WL 0.25 400 0.2 0.2 + 500 WL +0.25 350 -
tIS+tCK
+tIH 350 0.35 -450 0.35 WL -0.25 350 0.2 0.2
1)4) 1) 1) 1) 1)
tCK
ps
tCK tCK
ps ps
1)
1)4) 1)
tCK tCK
1)
min. (tCL, tCH) 600 600 2*tACmin
min. (tCL, tCH) 600 0.6 600
1)
tACmax
-
tACmax
-
ps ps
1) 1)4) 1) 1)4) 1) 1) 1) 1) 1) 1) 1)
Control and Addr. input pulse width (each input) 0.6
tCK
ps ps ps
tACmin
2 0 40 55 15
tACmax tACmax
12 70000 -
2*tACmin tACmax
tACmin
2 0 45 60 15
tACmax
12 70000 -
tCK
ns ns ns ns
Data Sheet
28
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings Table 21 AC Timing - Absolute Specifications -5 / -3.7 -5 DDR2-400 min. max. 7.8 3.9 1.1 0.60 -3.7 DDR2-533 min. 105 15 0.9 0.40 7.5 10 7.5 max. 7.8 3.9 1.1 0.60 ns ns s
1) 1) 1)
Symbol Parameter
Unit Notes
tREFI tRFC tRP tRPRE tRPST tRRD
Average Periodic Refresh Interval
0 C - 85 C 85C - 95C
105 15 0.9 0.40
Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command
1) 1) 1) 1)
tCK tCK
ns ns ns
x8 7.5 (1k page size) x16 10 (2k page size)
1)
tRTP tQH tQHS tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
2) CL = 3
Internal read to precharge command delay Data Output hold time from DQS Data hold skew factor Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to any valid command (other than NOP or Deselect)
7.5
1) 1)
tHP - tQHS 0.25 0.40 15 10 2 450 0.60 -
tHP-tQHS 0.25 0.40 15 7.5 2 6 - AL 2 400 0.60 ps
1) 1) 1) 1) 1) 1) 1)
tCK tCK
ns ns
tCK tCK tCK
ns
Exit active power-down mode to read command 6 - AL (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-read command Exit Self-Refresh to read command 2
1)
1)
tRFC + 10 200 -
tRFC +
10 200
1)5)
tCK
1)6)
1) For details and notes see the relevant INFINEON component datasheet 3) CL = 4 & 5 4) Timing definition and values for tIS, tIH, tDS and tDH may change due to actual JEDEC work. This may also effect the SPD code for these parameters 5) 0 C
TCASE 85 C
6) 85 C < TCASE 95 C
Data Sheet
29
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 22
ODT AC Electrical Characteristics and Operating Conditions (all speed bins) min. 3 max. Unit ODT to Power Down Mode Entry Latency ODT turn-off ODT turn-off delay ODT turn-off delay (Power-Down Modes) ODT turn-on ODT turn-on delay ODT turn-on (Power-Down Modes) ODT Power Down Exit Latency DDR2400/533
Symbol Parameter / Condition
tANPD tAOF tAOFD tAOFPD tAON tAOND tAONPD tAXPD
tCK
ns
tAC(min)
2.5
tAC(max) + 0.6 ns
2.5
tCK
ns
tAC(min) + 2 ns tAC(min)
2
2.5 tCK + tAC(max) + 1 ns ns
tAC(max) + 1 ns
2 2 tCK + tAC(max) + 1 ns -
tCK
ns
tAC(min) + 2 ns
8
tCK
Data Sheet
30
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
6
Table 23
SPD Codes
SPD Codes for HYS[64/72]T[32/64]000GU-3.7-A HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 02 00 01 3D 50 50 60 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 02 00 01 3D 50 50 60
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200U-444 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 02 00 01 3D 50 50 60 31
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns]
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 23 SPD Codes for HYS[64/72]T[32/64]000GU-3.7-A (cont'd) HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Description
PC2-4200U-444 Rev. 1.1 HEX 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 1D 1D 23 16
tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) 2B
Data Sheet
32
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 23 SPD Codes for HYS[64/72]T[32/64]000GU-3.7-A (cont'd) HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 E1 C1 00 xx 37 32 54 36 34 30 30 30 47 55 33 2E 37 41 20 20 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 CF C1 00 xx 36 34 54 36 34 30 30 30 47 55 33 2E 37 41 20 20
Label Code JEDEC SPD Revision Byte# 55 56 57 58 59 60 61 62 63 64 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Description T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16
PC2-4200U-444 Rev. 1.1 HEX 36 1C 30 00 00 00 00 11 B9 C1 00 xx 36 34 54 33 32 30 30 30 47 55 33 2E 37 41 20 20
65 - 71 JEDEC ID Code of Infineon (2 - 8)
Data Sheet
33
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 23 SPD Codes for HYS[64/72]T[32/64]000GU-3.7-A (cont'd) HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 96 97 98 128255 Description Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) BLANK
PC2-4200U-444 Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF
99 -127 Not Used
Data Sheet
34
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 24
SPD Codes HYS[64/72]T128020GU-3.7-A HYS64T128020GU-3.7-A HYS72T128020GU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 02 00 01 3D 50 50 60 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200U-444 Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 02 00 01 3D 50 50 60
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns]
35
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 24 SPD Codes HYS[64/72]T128020GU-3.7-A (cont'd) HYS64T128020GU-3.7-A HYS72T128020GU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Data Sheet Description
PC2-4200U-444 Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 36
tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 24 SPD Codes HYS[64/72]T128020GU-3.7-A (cont'd) HYS64T128020GU-3.7-A HYS72T128020GU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 E2 C1 00 xx 37 32 54 31 32 38 30 32 30 47 55 33 2E 37 41 20 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 55 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Data Sheet Description T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 37
PC2-4200U-444 Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 D0 C1 00 xx 36 34 54 31 32 38 30 32 30 47 55 33 2E 37 41 20
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 24 SPD Codes HYS[64/72]T128020GU-3.7-A (cont'd) HYS64T128020GU-3.7-A HYS72T128020GU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 96 97 98 99 -127 128-255 Description Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not Used BLANK
PC2-4200U-444 Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF
Data Sheet
38
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 25
SPD Codes for HYS[64/72]T[32/64]000HU-3.7-A HYS64T32000HU-3.7-A HYS64T64000HU-3.7-A HYS72T64000HU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 02 00 01 3D 50 50 60 3C Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 02 00 01 3D 50 50 60 3C
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200U-444 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 02 00 01 3D 50 50 60 3C 39
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRP.min [ns]
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 25 SPD Codes for HYS[64/72]T[32/64]000HU-3.7-A (cont'd) HYS64T32000HU-3.7-A HYS64T64000HU-3.7-A HYS72T64000HU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 34 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 34
Label Code JEDEC SPD Revision Byte# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Description
PC2-4200U-444 Rev. 1.1 HEX 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B 1D 1D 23 16 36
tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W)
Data Sheet
40
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 25 SPD Codes for HYS[64/72]T[32/64]000HU-3.7-A (cont'd) HYS64T32000HU-3.7-A HYS64T64000HU-3.7-A HYS72T64000HU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 1E 20 00 00 00 00 11 E1 C1 00 xx 37 32 54 36 34 30 30 30 48 55 33 2E 37 41 20 20 20 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 1E 20 00 00 00 00 11 CF C1 00 xx 36 34 54 36 34 30 30 30 48 55 33 2E 37 41 20 20 20
Label Code JEDEC SPD Revision Byte# 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Description T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17
PC2-4200U-444 Rev. 1.1 HEX 1C 30 00 00 00 00 11 B9 C1 00 xx 36 34 54 33 32 30 30 30 48 55 33 2E 37 41 20 20 20
Data Sheet
41
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 25 SPD Codes for HYS[64/72]T[32/64]000HU-3.7-A (cont'd) HYS64T32000HU-3.7-A HYS64T64000HU-3.7-A HYS72T64000HU-3.7-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 20 2x xx xx xx xx xx xx xx 00 FF Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 20 2x xx xx xx xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 90 91 92 93 94 95 96 97 98 99 -127 Description Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not Used
PC2-4200U-444 Rev. 1.1 HEX 20 2x xx xx xx xx xx xx xx 00 FF
128-255 BLANK
Data Sheet
42
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 26
SPD Codes for HYS[64/72]T128020HU-3.7-A HYS64T128020HU-3.7-A HYS72T128020HU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 02 00 01 3D 50 50 60 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200U-444 Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 02 00 01 3D 50 50 60
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns]
43
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 26 SPD Codes for HYS[64/72]T128020HU-3.7-A (cont'd) HYS64T128020HU-3.7-A HYS72T128020HU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Data Sheet Description
PC2-4200U-444 Rev. 1.1 HEX 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E 1E 24 17 44
tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 26 SPD Codes for HYS[64/72]T128020HU-3.7-A (cont'd) HYS64T128020HU-3.7-A HYS72T128020HU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 E2 C1 00 xx 37 32 54 31 32 38 30 32 30 48 55 33 2E 37 41 20 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 55 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Data Sheet Description T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 45
PC2-4200U-444 Rev. 1.1 HEX 34 1E 20 00 00 00 00 11 D0 C1 00 xx 36 34 54 31 32 38 30 32 30 48 55 33 2E 37 41 20
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 26 SPD Codes for HYS[64/72]T128020HU-3.7-A (cont'd) HYS64T128020HU-3.7-A HYS72T128020HU-3.7-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 96 97 98 99 -127 128-255 Description Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not Used BLANK
PC2-4200U-444 Rev. 1.1 HEX 20 20 2x xx xx xx xx xx xx xx 00 FF
Data Sheet
46
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 27
SPD Codes for HYS[64/72]T32000GU-5-A HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 02 00 01 50 60 50 60 3C Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 40 00 05 50 60 00 82 08 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200U-333 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRP.min [ns]
47
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 27 SPD Codes for HYS[64/72]T32000GU-5-A (cont'd) HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B
Label Code JEDEC SPD Revision Byte# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Description
PC2-3200U-333 Rev. 1.1 HEX 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 23 1D 19 1C 16 2E 1A 48
tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B)
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 27 SPD Codes for HYS[64/72]T32000GU-5-A (cont'd) HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 1E 00 00 00 00 11 35 C1 00 xx 37 32 54 36 34 30 30 30 47 55 35 41 20 20 20 20 20 20 2x Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 1E 00 00 00 00 11 23 C1 00 xx 36 34 54 36 34 30 30 30 47 55 35 41 20 20 20 20 20 20 2x
Label Code JEDEC SPD Revision Byte# 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2- 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code 49
PC2-3200U-333 Rev. 1.1 HEX 2D 00 00 00 00 11 0B C1 00 xx 36 34 54 33 32 30 30 30 47 55 35 41 20 20 20 20 20 20 2x
Data Sheet
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 27 SPD Codes for HYS[64/72]T32000GU-5-A (cont'd) HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX xx xx xx xx xx xx xx 00 FF 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E Rev. 0.87, 2004-06 09122003-GZEK-H4J6 HYS72T128020GU-5-A
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX xx xx xx xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 92 93 94 95 96 97 98 99 -127 128-255 Table 28 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not Used BLANK SPD Codes for HYS[64/72]T128020GU-5-A
PC2-3200U-333 Rev. 1.1 HEX xx xx xx xx xx xx xx 00 FF
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses
PC2-3200U-333 Rev. 1.1 HEX 80 08 08 0E
Data Sheet
50
HYS64T128020GU-5-A
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 28 SPD Codes for HYS[64/72]T128020GU-5-A (cont'd) HYS64T128020GU-5-A HYS72T128020GU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 0A 61 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Description Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200U-333 Rev. 1.1 HEX 0A 61 40 00 05 50 60 00 82 08 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
Data Sheet
51
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 28 SPD Codes for HYS[64/72]T128020GU-5-A (cont'd) HYS64T128020GU-5-A HYS72T128020GU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Description
PC2-3200U-333 Rev. 1.1 HEX 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG
Data Sheet
52
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 28 SPD Codes for HYS[64/72]T128020GU-5-A (cont'd) HYS64T128020GU-5-A HYS72T128020GU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 00 00 11 36 C1 00 xx 37 32 54 31 32 38 30 32 30 47 55 35 41 20 20 20 20 20 2x xx xx Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Description TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year
PC2-3200U-333 Rev. 1.1 HEX 00 00 11 24 C1 00 xx 36 34 54 31 32 38 30 32 30 47 55 35 41 20 20 20 20 20 2x xx xx
Data Sheet
53
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 28 SPD Codes for HYS[64/72]T128020GU-5-A (cont'd) HYS64T128020GU-5-A HYS72T128020GU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX xx xx xx xx xx 00 FF HYS64T64000HU-5-A 512 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 60 Rev. 0.87, 2004-06 09122003-GZEK-H4J6 HYS72T64000HU-5-A
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 94 95 96 97 98 Description Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4)
PC2-3200U-333 Rev. 1.1 HEX xx xx xx xx xx 00 FF
99 -127 Not Used 128-255 BLANK Table 29 SPD Codes for HYS[64/72]T[32/64]000HU-5-A HYS64T32000HU-5-A 256 MB x64
Product Type
Organization
1 Rank (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Rev. 1.1 HEX 80 08 08 0D 0A 60
PC2-3200U-333
Data Sheet
54
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 29 SPD Codes for HYS[64/72]T[32/64]000HU-5-A (cont'd) HYS64T32000HU-5-A HYS64T64000HU-5-A HYS72T64000HU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 40 00 05 50 60 00 82 08 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15
Label Code JEDEC SPD Revision Byte# 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Data Sheet Description Data Width Not used Interface Voltage Level
PC2-3200U-333 Rev. 1.1 HEX 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 55
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns]
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 29 SPD Codes for HYS[64/72]T[32/64]000HU-5-A (cont'd) HYS64T32000HU-5-A HYS64T64000HU-5-A HYS72T64000HU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 00 00 11 35 Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 00 00 11 23
Label Code JEDEC SPD Revision Byte# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Data Sheet Description
PC2-3200U-333 Rev. 1.1 HEX 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 0B 56
tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 29 SPD Codes for HYS[64/72]T[32/64]000HU-5-A (cont'd) HYS64T32000HU-5-A HYS64T64000HU-5-A HYS72T64000HU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX C1 00 xx 37 32 54 36 34 30 30 30 48 55 35 41 20 20 20 20 20 20 2x xx xx xx xx xx xx xx Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX C1 00 xx 36 34 54 36 34 30 30 30 48 55 35 41 20 20 20 20 20 20 2x xx xx xx xx xx xx xx
Label Code JEDEC SPD Revision Byte# 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Data Sheet Description JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) 57
PC2-3200U-333 Rev. 1.1 HEX C1 00 xx 36 34 54 33 32 30 30 30 48 55 35 41 20 20 20 20 20 20 2x xx xx xx xx xx xx xx
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 29 SPD Codes for HYS[64/72]T[32/64]000HU-5-A (cont'd) HYS64T32000HU-5-A HYS64T64000HU-5-A HYS72T64000HU-5-A 512 MB x72 1 Rank (x8) Rev. 1.1 HEX 00 FF 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 50 60 Rev. 0.87, 2004-06 09122003-GZEK-H4J6 HYS72T128020HU-5-A
Product Type
Organization
256 MB x64 1 Rank (x16)
512 MB x64 1 Rank (x8) Rev. 1.1 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 99 -127 128-255 Table 30 Description Not Used BLANK SPD Codes for HYS[64/72]T128020HU-5-A
PC2-3200U-333 Rev. 1.1 HEX 00 FF
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200U-333 Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 50 60
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
58
Data Sheet
HYS64T128020HU-5-A
Product Type
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 30 SPD Codes for HYS[64/72]T128020HU-5-A (cont'd) HYS64T128020HU-5-A HYS72T128020HU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 02 82 08 08 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Description Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes Component Attributes
PC2-3200U-333 Rev. 1.1 HEX 00 82 08 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Data Sheet
59
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 30 SPD Codes for HYS[64/72]T128020HU-5-A (cont'd) HYS64T128020HU-5-A HYS72T128020HU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 00 00 11 36 C1 00 xx Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 - 71 72 Description Analysis Characteristics
PC2-3200U-333 Rev. 1.1 HEX 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 00 00 11 24 C1 00 xx
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location
Data Sheet
60
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 30 SPD Codes for HYS[64/72]T128020HU-5-A (cont'd) HYS64T128020HU-5-A HYS72T128020HU-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 37 32 54 31 32 38 30 32 30 48 55 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00 FF Rev. 0.87, 2004-06 09122003-GZEK-H4J6
Product Type
Organization
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 -127 128-255 Description Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not Used BLANK
PC2-3200U-333 Rev. 1.1 HEX 36 34 54 31 32 38 30 32 30 48 55 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00 FF
Data Sheet
61
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
7
7.1
0.1 A B C
Package Outlines
Raw Card A
133.35 128.95 0.1
0.3 C
1.27 0.1
4
1
4 0.1 2.5 0.1 5 0.1 63 0.1 55 0.1
120
30
2.7 MAX.
A 1.5 0.1
3.8
121
240
2.3 0.1 10 0.1
3 MIN.
Detail of contacts
0.2
1
0.8 0.2
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 8
Package Outline L-DIM-240-1
Data Sheet
62
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
17.8 0.1
B
GLD09652
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
7.2
0.1 A B C
Raw Card B
133.35 128.95 0.1
0.4 C
1.27 0.1
4
1
4 0.1 2.5 0.1 5 0.1 63 0.1 55 0.1
120
30
4 MAX.
A 1.5 0.1
3.8
121
240
2.3 0.1 10 0.1
3 MIN.
Detail of contacts
0.2
1
0.8 0.2
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 9
Package Outline L-DIM-240-2
Data Sheet
63
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
17.8 0.1
B
GLD09653
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
7.3
0.1 A B C
Raw Card C
133.35 128.95 2.7 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4 1.27 0.1
A 1.5 0.1
3.8
121
240
2.3 0.1 10
30
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 10
Package Outline L-DIM-240-3
Data Sheet
64
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
17.8
B
GLD09654
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 31 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 32 and for components in Table 33. Table 31 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 32 Field 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
5 6 7 8 9
Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type
0 .. 9 0, 2, 4 0 .. 9 A .. Z S M R U
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Data Sheet
65
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U-[3.7/5]-A 512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Table 33 Field 1 2 3 4
DDR2 DRAM Nomenclature Description INFINEON Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G Coding Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533 DDR2-400
5+6
Number of I/Os
40 80 16
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F
10 11
-3.7 -5
Data Sheet
66
Rev. 0.87, 2004-06 09122003-GZEK-H4J6
www.infineon.com
Published by Infineon Technologies AG

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